Monday, May 5, 2008

DFT Audit

DFT (Design for Testability) techniques have been used at least since the early days of electric/electronic data processing equipment. Early examples from the 1940s/50s are the switches and instruments that allowed an engineer to “scan” (i.e., selectively probe) the voltage/current at some internal nodes in an analog computer [analog scan].

Over the years the industry has developed and used large variety formal guidelines for desired and/or mandatory DFT circuit modifications. As well large variety of commercial DFT software tools also developed. Many PCB Layout tools provide the feature in the name of “DFT Audit”.

This embedded tool allows us to perform analysis and verification as well as Test point coverage and reporting before we release a board for fabrication. DFT Audit enables the design-for-test criteria earlier in the product design cycle by performing testability analysis during PCB and advanced package design.

By incorporating DFT Audit into your design process, one can dramatically decrease time-to-volume production, reduce costs, and improve product quality.

Some of the common features provided by this DFT Audit are,
•Analysis of complex testpoint-keepout areas
•Batch and interactive DRC checks
•Generates test point coverage reports for design review
•Interactive DFT Check Algorithms

One challenge for the industry is keeping up with the rapid advances in chip technology (I/O count- Speed-Size and Power) without being forced to continually upgrade the test equipment. Modern DFT techniques, hence, have to offer options that allow next generation chips and assemblies to be tested on existing test equipment and/or reduce the requirements/cost for new test equipment.

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